Semiconductor device performance variability and yield loss can be caused by layout-dependent effects related to pattern printability. Examples of such layout-dependent effects include line end shortening, MOSFET gate flaring, MOSFET gate necking, etc. The criticality of a layout pattern with regard to adverse layout-dependent effects is traditionally characterized by the geometric deviation of the as-printed layout pattern from the ideal layout pattern, based on a real image. Also, the criticality of a layout pattern can be characterized by its sensitivity to a particular fabrication process, wherein sensitivity is defined by a proclivity toward non-ideal geometric deviation due to the particular fabrication process conditions.
In nanometer scale technologies, device performance variability due to layout-dependent effects could cause functional and parametric yield losses. Therefore, maintaining performance and process margin across different layout styles and environments is a critical issue for nanometer scale technologies. The criticality of performance and process margin are driven by more aggressive sub-wavelength lithography and device scaling, combined with increasing operating frequencies into the multi-GHz range, which contribute to increase the sensitivity of circuit performance to layout configuration. Additionally, newer technologies are giving rise to new phenomena of significance, such as neighborhood dependent and systematic within-die variations in polysilicon critical dimension (CD), two-dimensional environment effects on printability, narrow width effects, etc.